Referring to the Moore law which empirically foresees the doubling of integration of the components in the electronic industry every two years, the current developments of electronics are often mentioned as following two complementary directions. One development consists of More Moore miniaturisation, i.e. continually reducing the dimensions of the elementary components. Simultaneously, the More than Moore diversification defines the trend consisting in integrating more and more different functionalities in the same chip, whatever the degree of miniaturisation. Both developments are simultaneous and concern a wide range of technologies and methods which are studied by all the major research and development services. Among the methods studied a three-dimension 3D integration architecture consists in vertically stacking electronic components, by superimposing chips and/or wafers and by establishing short electric connections between such components, directly through the layers. 3D integration requires to control the electric connections between the various vertically stacked chips. It must face many challenges, and more particularly the complex design, the problems entailed in thermal dissipation, the absence of standardisation, reliability, the definition of test strategies adapted to stacked circuits.
The two types of connectics generally used to bring the signals to the inputs and outputs of a circuit are the “wire bonding” and the bonding of “flip chips”. Several approaches are available for connecting several chips in the same packaging, without choosing the solution of external wiring. Among all such integration approaches, the common vector lies in the utilisation of through electric vias to bond the electric connections from a first face to a second face without using a wire external to the chip. Two options are provided for executing the intra-chip connections. The first option consists in implementing the through electric vias directly into one of the active chips of the stack. The second one which is more commonly used, consists in designing a mechanically autonomous microelectronic device or passive substrate, also called an interposer, which connects two “sandwich” implemented chips around the device. Both systems communicate, through the latter, using an internal routing and through electric vias which connect the front face and the rear face of the interposer. When several components are positioned side by side on the same mechanically autonomous microelectronic device, this is called 2.5D integration.
Silicon interposers have recently been developed in the industry. However, a certain number of drawbacks makes the use thereof difficult. As a matter of fact, the current interposers are not mechanically stable because of their low thickness. Generally speaking, they are rather thin since they are provided with vertical electric connections (of the TSV type, i.e. the acronym for Through Silicon Via or the acronym TGV for Through Glass Via), to enable the passage of the electric signal from an upper face (chip interconnects) to a lower face (substrate interconnects).
In the case of silicon, the current advanced manufacturing technology makes it possible to form through electric vias having a form factor of about 10:1. Considering the electric requirements and the cost of filling the copper-made through electric vias, many industrialists have selected a practical diameter for the through electric vias, of the order of 10 microns. A form factor of 10 to 1, means that the length of the through electric vias and, consequently the thickness of the interposers are generally limited to 80 to 120 microns. Over the next few years, larger form factors will have to be aimed at for the through electric vias; a form factor of, for instance, 20 to 1 is even a goal for some industrialists. Even with an improved form factor, the length of the electric vias however requires the production and the utilisation of a very thin interposer, consequently having an inherent mechanical brittleness.
As silicon interposers have a major drawback in that they are relatively thin and thus mechanically fragile, electric measurements and tests are more and more difficult and may become soon almost impossible. Interposers will probably be tested prior to assembling, and the cost of non-compliance will thus be very high. Few companies are still capable of manufacturing both chips and interposers today. When only one manufacturer is involved in the production of chips and interposers, the issues of recovering non-compliance costs can be dealt with internally and can be more easily controlled. But as they do not know how to perform testing and quantifying, it is very difficult for two distinct manufacturing companies to agree on non-compliance terms and conditions. This means that a company producing chips and another company producing substrates will non longer cooperate, which will unavoidably affect the production lines of the companies not having a manufacturing unit, as well as the development costs.
The manufacturing process of a silicon interposer is currently difficult (and thus costly). One of the main reasons (in addition to high costs) is that the current method requires the handling and processing of very thin wafers. Advanced technologies are used when handling wafers, when the very thin silicon interposer remains attached to the silicon or glass substrate using temporary bonding. Bonding, and unbonding, which are followed by the handling of very thin components, thus become very difficult. Many alternative bonding and unbonding techniques exist, for instance the so-called laser release, temperature release, multi-layer glue, spin-on, laminate techniques. Generally speaking, the industry however was unable to agree on a reference technique; each technique has drawbacks.
Whatever the integration method selected for manufacturing silicon interposers, the final device is very thin. As the interposer is exposed to different stresses on each one of its faces (the upper face and the lower face have a very different structures and apparently require different interconnections locations), the silicon interposer tends to bend and then to deform. The larger the surface of the interposer, the worst the bending and deformation thereof.This is the main technical challenge when designing interposers today, before cost.
The present invention makes it possible to remedy all or at least some of the drawbacks of the current techniques. The invention provides for producing a mechanically stable and autonomous microelectronic device complying with the needs of the production line.